INFORMATICA International Journal Main Page Editorial Board Abstracting/Indexing Instructions to Authors Subscription Information Contents Author Index Papers in Production		INFORMATICA, 2003, Vol. 14, No. 2, 135-154 © Institute of Mathematics and Informatics, ISSN 0868-4952 Identifying Legal and Illegal States in Synchronous Sequential Circuits Using Test Generation Eduardas BAREISA, K\c{e}stutis MOTIEJUNAS, Rimantas SEINAUSKAS Department of Software Engineering, Kaunas University of Technology Student 50-406, LT-3028 Kaunas, Lithuania E-mail: kestas@soften.ktu.lt Abstract Identifying legal and illegal states significantly reduces computational complexity of ATPG. A unified framework for identification of the legal and illegal states is presented. Most known methods for identification of the legal and illegal states are interpretable within this framework. New theorems and the resulting procedures for identifying exact collection of legal or illegal states of a circuit are presented. Experimental results demonstrate that exact collection of legal states for some circuits is significantly smaller than collections obtained by backward state search algorithm and by algorithm based on combinational ATPG theorems. The use of the exact collection of legal states allows identifying more undetectable faults. The proposed procedure for identifying of the exact collection of legal states starts from any state of the circuit, builds initially an enlarged collection of legal states and converges rapidly to the exact solution. Keywords: sequential circuits, legal and illegal states, detectability of faults To preview Lithuanian abstract see full article text To preview full article text in PDF format click here You could obtain free Acrobat Reader from Adobe
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